As the conventional semiconductor transistor scaling approaches the physical limits of conventional material and device structure, atomic thin channels stacking in the vertical directions such as complementary FET (CFET) are regarded as the future technology route beyond 2 nm node. Moreover, 3D integration becomes more and more important toward low power high efficiency data-centric computing, back-end-of-line (BEOL) compatible transistors for logic and memory applications with high performance and low power face tremendous opportunities and challenges as well. In this talk, material and device progress aiming at the performance and power bottlenecks will be discussed including 2D CFET logic, oxide based capacitorless DRAM and ferroelectric HfO2 memory. The key issues such as the scaling capability, on-state performance and off-state leakage current will be addressed, as well as proof-of-concept circuit demonstrations.